Non-volatile random access memories (RAM's) are used in various systems. For example, they are used as a system configuration data memory in personal computer, a data register for suspend/resume function, a program memory for error checking, and a data memory for IC card. The memory capacity required for such non-volatile memories is not very large and may often be sufficient to range from several kilobits to several hundreds kilobits.
When such a non-volatile RAM of a small capacity and a logic LSI such as a gate array or a microprocessor can be formed together in the same semiconductor substrate, production costs and the size of the device can be greatly reduced. However, due to the difference between the respective production processes, it is difficult to form them in a mixed manner together in the same semiconductor substrate. For example, a typical non-volatile RAM is an EEPROM memory of stacked gate structure in which a floating gate and a control gate are stacked, but such a memory cannot be manufactured through the standard complementary metal oxide semiconductor (CMOS) logic LSI process. That is because the standard CMOS process employs a one-layer polysilicon deposition step whereas the ordinary stacked gate ROM's require two polysilicon deposition steps for the floating gate and control gate. The ordinary stacked gate ROM's further require a step of depositing a very thin oxide layer between the two gates that is not used in the standard CMOS process.
Consequently, it was conventional in the prior art to form the non-volatile RAM and logic LSI in separate chips which are subsequently combined, or to modify the standard logic LSI process to allow the non-volatile RAM and logic LSI to be formed on the same chip. However, these methods are costly. Modifying the standard process also has a drawback in that it not only complicates the process but also requires strict process control.
Japanese Published Unexamined Patent Application (PUPA) 3-101168 discloses a non-volatile memory with a low power consumption formed through the CMOS process. In this patent application, between a program bit line and a ground potential are connected in series a first PMOS transistor, a second PMOS transistor, and an NMOS transistor. A floating gate is formed by the gates of the second PMOS and the NMOS transistors which are connected in common. The gate of the first PMOS transistor is connected to a word line. The common junction between the second PMOS and the NMOS transistors is connected to a read bit line. When writing data, the program bit line and the word line are simultaneously selected to turn on the first PMOS so that the positive potential on the program bit line is coupled to the second PMOS transistor. In this state, the floating gate and the drain of the NMOS transistor assume a positive potential and inject hot electrons into the floating gate.
However, the method disclosed in PUPA 3-101168 is not practical. That is, to generate hot electrons in the NMOS transistor, a high voltage must be applied to the drain of the NMOS transistor. However, since the NMOS transistor is connected in series with the two PMOS transistors which inherently have low conductance, a considerably large voltage must be applied to the program bit line to generate a required voltage at the drain of the NMOS. On the other hand, widening the channel width and thus enlarging the device size to increase conductance results in a larger gate capacitance of the PMOS transistors. The voltage of the floating gate is determined by the gate capacitance ratio of the PMOS to the NMOS transistor. Thus an increase in the gate capacitance of the PMOS transistor raises the floating gate voltage. As a result, the conduction of the PMOS falls, and the drain voltage of the NMOS falls. Consequently, the technique disclosed in the above patent application requires, in practice, not only a large writing voltage but also the fulfillment of contradictory requirements and thus is not practical. Besides, three FET's per cell are required.